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Digital IP Cores ..::.. Sydaap Technologies Pvt.Ltd Untitled Document
  Digital IP Cores

Advanced Encryption Standard (AES) IP core implements Rijndael encryption and decryption algorithm as specified in Federal Information Processing Standard (FIPS) 197 from the National Institute of Standards and Technology (NIST). The parameterized cores can be compiled for either encryption or decryption or both encryption and decryption function and key expansion, supporting any or all proposed key sizes (128/192/256-bit). Core provide user the greatest possible flexibility due to the option of compile time parameters for configuring the core. These cores are designed to be simple to use and can be integrated into any AES design with minimum effort. Verilog source code or ASIC/FPGA netlist is available for the fully functional synchronous AES core. They support all cipher modes (ECB, CBC, CFB1, CFB8, CFB128, OCB and CTR) of AES defined in SP800-38A with or without key expander.

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LDPC Coder/Decoder

The LDPC encoder generates code words of the specified block length n for an binary information sequence of length k based on Parity Check Matrix (PCM) that has very low density of 1’s per rows and columns. The remaining elements of PCM are all 0’s. This LDPC has code rate of k/n and block length of n. The dimension of the PCM is (n-k)xn. The LDPC decoder IP core implements the min-sum-offset algorithm to decode LDPC codes.
The core accepts soft information that is stored in memory and generates decoded information bits. The maximum number of iterations used in the decoding of LDPC codes is fed as input. Decoding is stopped when maximum iterations are reached or when code word is decoded without any errors.


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World’s First 64 Bit Floating Point FFT/IFFT  Hardware Accelerator for N = 4096

Sydaap develops world’s first 64-bit precision floating point Fast Fourier Transform/Inverse Fast Fourier Transform hardware accelerator module suitable for LTE-Advanced, OFDM and for all such standards that will evolve over the next decade.



Key Features:

  • 64 Bit Precision, Floating Point Arithmetic based on IEEE 754
  • Radix-2 implementation for samples up to N = 4096
  • Dynamically Re-configurable for multiple sample sizes from N = 2 to 4096.
  • Clock Frequency of  2.3 GHz with 28 nm technology
  • Throughput of one sample output for every clock cycle.
  • Initial Latency, Area and RAM size customized for specific customer requirements.

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3GPP Channel Estimator and Equalizer

3GPP Channel Estimator and Equalizer for LTE-Advanced and Beyond

Sydaap develops 3GPP Channel Estimator & Equalizer for LTE-Advanced and standards beyond. Implementation based on a proprietary algorithm and frame work, fully compliant to the requirements defined in 3gpp release 10 and sufficiently scalable for upcoming releases and similar standards.



Key Features:

  • Suitable for eNodeB Physical Layer controllers for Uplink-SCFDMA estimation.
  • Based on a proprietary algorithm adept at handling rapidly varying channels.
  • Support for single and multiple antenna configurations (SISO & MIMO up to 8x8).
  • Modulation schemes supported for QPSK, 16-QAM and 64-QAM.
  • Input Data type is fixed/floating Point. Internal computation is 64-bit floating point.
  • Clock Frequencies greater than 2 GHz with 28 nm technology.
  • Throughput of one symbol output for every clock cycle after the initial estimation latency.
  • Dynamically reconfigurable for statistical channel parameters, antenna configurations and modulation types.


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Turbo Decoder LTE-A

3GPP Turbo Decoder for LTE-Advanced and Beyond

Sydaap develops 3GPP Turbo Decoder for LTE-Advanced and standards beyond. Implementation based on a proprietary algorithm, fully compliant to the requirements defined in 3gpp standards. The performance metrics are sufficiently high to support multiple  applications.



Key Features:

  • Primarily built for LTE supporting: Rate  of 1/3 and Block lengths up to 6144
  • Based on a proprietary algorithm, a partially linear derivative of Log MAP.
  • Achieving Zero BER convergence with three iterations. Fourth iteration performance metric is sufficiently ahead of 3gpp requirements.
  • Achieving  throughputs of 440 Mb/s   for block lengths of 6144 at clock frequencies of 350 MHz
  • Parameters such as block length, window size and number of iterations maybe dynamically reconfigurable.


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